This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
In conventional memory cells, such as, e.g., 6T SRAM (static random access memory) cells, a bias of a low internal node may increase during a read operation, due to charge injection from bitline capacitance. In this case, if the bias rises above a switching point of internal inverters, the memory cell may become unstable, and the memory cell may inadvertently switch its state. This particular scenario may be referred to as a read disturb that may occur for an asserted wordline during a read or write operation. In some cases, this read disturb may occur for memory cells on the selected wordline during a read operation. In some other cases, this read disturb may occur for a row of memory cells on a selected wordline during a write operation.